Comparison between model based approach and hdl approach for a DDR3 controller

In an earlier post I described a simple architecture for creating a FIFO-like DDR3 controller using Vivado's block design integrator tool. This tool is of great use when interconnecting various IP Cores with standard interfaces as it was the case. This however is usually not the most optimal implementation for a given design.

The usage of the DataMover in the architecture mentioned previously still required a FSM written in HDL language to control the different commands and achive the desired behavior. That FSM dealed with data sizes, addresses and status reports to move data from the AXI-S to the AXI-MM domain and viceversa.

After a more detailed review of the AXI-MM protocol the FSM used to issue commands to the DataMover could be easily modified to instead handle the AXI-MM interface of the Xilinx's DDR IP Core and therefore eliminating the need of the DataMover, the AXI-Interconnect and the Block Design tool.

The following image represents the resource utilization for both approaches.

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Comparizon of resources utilization between both approaches

The case a) represents the utilization of the different blocks in the model based approach

  • Yellow: HDL Block to control the DataMover
  • Purple: DDR Controller Block with AXI-MM Interface
  • Red: DataMover Block
  • Green: AXI-Interconnect Block
  • Blue: Input and Output FIFOs for DDR Controller and extra logic for PCIe communication

The case b) represents the utilization of the different blocks in the HDL approach

  • Yellow: HDL Block to control the DataMover
  • Purple: DDR Controller Block with AXI-MM Interface
  • Blue: Input and Output FIFOs for DDR Controller and extra logic for PCIe communication
Resource
Slice LUTs 19181 12557
Slice Registers 19262 10262
Muxes 421 4134
Slices 8542 5017
LUT FF Pairs 25096 15534
Block RAM tiles 31.5 15.5
% of Design 80 % 70 %

HDL approach (b) uses in average only 70 % of the resources of the model based approach (a)

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